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Flash memory technologyCAMPARDO, Giovanni; MICHELONI, Rino.Proceedings of the IEEE. 2003, Vol 91, Num 4, issn 0018-9219, 154 p.Serial Issue

Improved flash memory grows in popularityLAWTON, George.Computer (Long Beach, CA). 2006, Vol 39, Num 1, pp 16-18, issn 0018-9162, 3 p.Article

Flash Storage MemoryLEVENTHAL, Adam.Communications of the ACM. 2008, Vol 51, Num 7, pp 47-51, issn 0001-0782, 5 p.Article

Novel program versus disturb window characterization for split-gate flash cellSUNG, Hung-Cheng; LEI, Tan Fu; HSU, Te-Hsun et al.IEEE electron device letters. 2005, Vol 26, Num 3, pp 194-196, issn 0741-3106, 3 p.Article

RNFTL: A Reuse-Aware NAND Flash Translation Layer for Flash MemoryYI WANG; DUO LIU; MENG WANG et al.ACM SIGPLAN notices. 2010, Vol 45, Num 4, pp 163-172, issn 1523-2867, 10 p.Conference Paper

An investigation of erase-mode dependent hole trapping in flash EEPROM memory cellHADDAD, S; CHI CHANG; WANG, A et al.IEEE electron device letters. 1990, Vol 11, Num 11, pp 514-516, issn 0741-3106, 3 p.Article

The Five-Minute Rule 20 Years Later (and How Flash Memory Changes the Rules)GRAEFE, Goetz.Communications of the ACM. 2009, Vol 52, Num 7, pp 48-59, issn 0001-0782, 12 p.Article

l'avènement des mémoires flash = The advent of the flash memoriesMARTIN, Gabriel.Recherche (Paris, 1970). 2004, Num 375, pp 84-85, issn 0029-5671, 2 p.Article

Test and repair of non-volatile commodity and embedded memories (NAND flash memory )SHIROTA, Riichiro.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1221Conference Paper

Using an ammonia treatment to improve the floating-gate spacing in split-gate flash memoryCHU, Wen-Ting; LIN, Hao-Hsiung; TU, Yeur-Luen et al.IEEE electron device letters. 2004, Vol 25, Num 9, pp 616-618, issn 0741-3106, 3 p.Article

What the Future Holds for Solid-State MemorySTRAUSS, Karin; BURGER, Doug.Computer (Long Beach, CA). 2014, Vol 47, Num 1, pp 24-31, issn 0018-9162, 8 p.Article

Constant-charge-injection programming for 10-MB/s multilevel AG-AND flash memoriesKURATA, Hideaki; SAEKI, Shunichi; KOBAYASHI, Takashi et al.2002 symposium on VLSI circuits. 2002, pp 302-303, isbn 0-7803-7310-3, 2 p.Conference Paper

Investigation of the soft-write mechanism in source-side injection flash EEPROM devicesVAN HOUDT, J. F; WELLEKENS, D; GROESENEKEN, G et al.IEEE electron device letters. 1995, Vol 16, Num 5, pp 181-183, issn 0741-3106Article

Second-Bit-Effect-Free Multibit-Cell Flash Memory Using Si3N4/ZrO2 Split Charge Trapping LayerGANG ZHANG; LEE, Seung-Hwan; CHANG HO RA et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 9, pp 1966-1973, issn 0018-9383, 8 p.Article

Optimising flash memory tunnel programmingIRRERA, Fernanda; FRISTACHI, Teodoro; CAPUTO, Domenico et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 405-410, issn 0167-9317, 6 p.Conference Paper

Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-k Trapping LayerGANG ZHANG; WANG, Xin-Peng; WON JONG YOO et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 12, pp 3317-3324, issn 0018-9383, 8 p.Article

Band-to-band tunneling induced substrate hot electron injection (BBISHE) to perform programming for NOR flash memoryWU, Meng-Yi; DAI, Sheng-Huei; LEE, Kung-Hong et al.Solid-state electronics. 2006, Vol 50, Num 3, pp 309-315, issn 0038-1101, 7 p.Article

Data retention of silicon nanocrystal storage nodes programmed with short voltage pulsesPUZZILLI, Giuseppina; IRRERA, Fernanda.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 4, pp 775-781, issn 0018-9383, 7 p.Article

A new non-volatile memory architecture embedding microbatteries to improve data retention criterionPOSTEL-PELLERIN, J; CHIQUET, P; LALANDE, F et al.Solid-state electronics. 2014, Vol 101, pp 79-84, issn 0038-1101, 6 p.Conference Paper

Embedded Flash on a Low-Power 65-nm Logic TechnologyFONG, S; ARIYOSHI, J; EMA, T et al.IEEE electron device letters. 2012, Vol 33, Num 9, pp 1261-1263, issn 0741-3106, 3 p.Article

New Read Schemes Using Boosted Channel Potential of Adjacent Bit-Line Strings in NAND Flash MemoryJOE, Sung-Min; JEONG, Min-Kyu; KANG, Myounggon et al.IEEE electron device letters. 2012, Vol 33, Num 8, pp 1198-1200, issn 0741-3106, 3 p.Article

Cone-Type SONOS Flash MemoryGIL SUNG LEE; JUNG HOON LEE; WAN DONG KIM et al.IEEE electron device letters. 2009, Vol 30, Num 12, pp 1332-1334, issn 0741-3106, 3 p.Article

Protein-mediated nanocrystal assembly for flash memory fabricationSHAN TANG; CHUANBIN MAO; YUERAN LIU et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 3, pp 433-438, issn 0018-9383, 6 p.Article

Highly scalable ballistic injection AND-type (BiAND) flash memoryWU, Meng-Yi; DAI, Sheng-Huei; HU, Shu-Fen et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 1, pp 109-111, issn 0018-9383, 3 p.Article

Algorithms and data structures for flash memoriesGAL, Eran; TOLEDO, Sivan.ACM computing surveys. 2005, Vol 37, Num 2, pp 138-163, issn 0360-0300, 26 p.Article

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